1. Field of the Invention
This invention relates to a memory device having a data pre-fetch function for continuously fetching a plurality of data, for one supplied address, and writing those data simultaneously to internal memory cells, and particularly to a memory device capable of making write operations faster.
2. Description of the Related Art
Clock-synchronized memory devices such as SDRAMs fetch data and addresses, output data, and perform internal operations in synchronization with a clock signal. The DDR-SDRAM (double data rate synchronous DRAM) has been proposed for making such SDRAM operations even faster. The DDR-SDRAM, more specifically, performs the operations mentioned above synchronized with both the rising edge and the falling edge of the clock signal.
Meanwhile, in memory devices, multiple bit data pre-fetch functions are provided for performing read and write operations on a plurality of data internally for one address. Accordingly, in the write mode of such a DDR-SDRAM, a write command signal and address are fetched in synchronization with the rising edge of the clock signal, and then, in synchronization with the rising edge and the falling edge of the clock signal, a plurality of write data are fetched. Then, after all data have been fetched, the address decoder and write circuit begin operating.
In FIG. 16 is given a circuit configuration diagram of a column system in a conventional memory device. In FIG. 17 is given a timing chart wherein are indicated problem points in a conventional write mode. In FIG. 16 there is an address buffer 10 that fetches addresses A0-A13, a delay circuit 44 for delaying those addresses, a redundancy checking circuit 46 for making comparisons with redundant addresses, and decoder circuits 48 and 50 for inputting and decoding redundancy checking signals and an address .phi.46. Also provided are an input buffer 24 for inputting data, delay circuits 25 and 27 for delaying those data, respectively, and a write amp 52 for amplifying the delayed data Data1 and Data2 and supplying them to data buses DB.
In the example in FIG. 16, the decoder circuitry includes an ordinary decoder circuit 48 and a redundancy decoder circuit 50. In the example in FIG. 16, moreover, a 2-bit data pre-fetch function is provided, and a memory cell array (not shown) is made up of an odd-numbered address side and an even-numbered address side. Accordingly, the decoder circuits 48 and 50 output an odd-side column selection signal CL.sub.O and an even-side column selection signal CL.sub.E. Similarly, the write amp 52 supplies data for an odd-side data bus DB.sub.O and an even-side data bus DB.sub.E, respectively.
As represented in the timing chart for the write mode in FIG. 17, a write-destination address Add1 is supplied simultaneously with the supply of a write command WR1 at the rising edge t0 of the clock signal. Then, in synchronization with the rising edge t2 of the clock signal after one clock period defined by a data latency=1, the first datum Data1 is supplied, and, in synchronization with the following clock signal falling edge t3, the second datum Data2 is supplied. At the clock signal falling edge t3 where the second bit of data is fetched, the redundancy checking operation RDD begins, and, following after that, the decoder operation DEC is started. From the point in time where the decoder operation DEC ends up until the time that the next redundancy checking operation RDD ends constitutes an address defining time T.sub.WADD for defining the address Add1 for the write command.
Also, the data Data1 and Data2 are amplified by the write amp 52 from the falling edge t3 of the clock signal where the last datum Data2 is supplied. That being so, from the point in time where this write amp 52 operation ends up until the end of the write amp 52 operation in the next cycle constitutes a data defining time T.sub.WDA, and the status during that time interval is one wherein data are supplied on the data bus.
Therefore, in the example in FIG. 17, the time interval wherein the data defining time T.sub.WDA and the address defining time T.sub.WADD overlap becomes the write enabled time T.sub.WEN. It is necessary for the column selection signal CL to be supplied during this time period, and a CL activating signal .phi..sub.CL that controls the timing of the generation of the column selection signal CL is generated within the write enabled time T.sub.WEN. In order to effect the operational timing described above, the delay circuit 44 is provided in the address system, and the delay circuits 25 and 27 are provided in the data system. These delay circuits, respectively, are configured by flip-flops which operate in synchronization with the clock signal. More specifically, the rising edge of the clock signal constitutes timing where the clock signal phase is 0.degree., and the falling edge of the clock signal constitutes timing where the clock signal phase is 180.degree..
As described in the foregoing, when a 2-bit data pre-fetch function is provided, the write amp 52, which is a data-system circuit, cannot be operated until after all of the 2 bits of data have been fetched. Accordingly, the start of the write amp operation is at the falling edge t3 of the clock signal after 2 bits of data are fetched, after the clock cycle with the data latency (=1) from the supply of the write command WR1. Similarly, in conventional circuitry, the circuits in the address system also begin their operations from the falling edge t3 of the clock signal just as in the data system. That being so, the redundancy checking operation begins with a clock signal t3 timing, and the decoder operation is performed after that. As a result, the write enabled time T.sub.WEN does not come until after the clock signal time t4, whereupon substantially long time is consumed until write completion.
This kind of delay in the write timing is not compatible with implementing a double-rate clock scheme to achieve faster speeds, and further the impartation of a multiple-bit data pre-fetch function.
Furthermore, depending on the architecture of the memory device, the operating period of the redundancy checking circuit and the decoder operation sometimes becomes longer. When that is the case, it sometimes happens that the T.sub.WEN, in the region where the address defining time T.sub.WADD and the data defining time T.sub.WDA overlap, becomes even narrower. In such cases, when the clock is run at higher speeds, it may be anticipated that it will become impossible to secure the write enabled time T.sub.WEN unless the timing of the start of operation in each circuit is optimized.
Thereupon, an object of the present invention is to provide a clock-synchronized memory device wherewith write operations can be made faster than in conventional examples.
Another object of the present invention is to provide a clock-synchronized memory device wherewith appropriate write operations can be performed with a high-frequency clock.
Yet another object of the present invention is to provide a clock-synchronized memory device wherewith write operations are fast and appropriate write operations can be performed, even with a high-frequency clock.